资源列表
clock
- 用verilog语言编写的一个电子钟。能够显示时分秒，具有清零，设置时间的功能。-Verilog language with an electronic clock. Can display minutes and seconds, with a clear, set the time function.
conter
- code of a counter with vhdl very hey descr iption language it counts from 0 to 255
adc7923
- 完成AD7923的控制和数据读取,AD7923为四路AD，SPI输出接口-Complete the AD7923 control and data read, AD7923 as four-way AD, SPI output interface
32-float-point-adder
- 32位浮点加法器。我第一次上载源码你就放过我吧，我就是想看一看加法器应该怎么做。-Floating point adder
keyboard
- 键盘输入实验 实验要求：利用实验板上的4×3小键盘，当检测到有键按下时，读取按键值并在LED数码管中显示该值。-Keyboard input test test requirements: use of experimental board 4 × 3 keypad when a key is detected, the read key value and the LED digital display the value.
FIR
- fir filter design using vhdl codes
motor-positioning-control-vhdl
- 步进电机定位控制系统VHDL程序与仿真,绝对能用,经本人毕设测试!-Stepper motor positioning control system and simulation of VHDL program, absolutely can, after I completed the test set!
AD7982VHDL
- AD7982 的控制和读写程序 师姐用VHDL编的，编译无错误！-AD7982 and written procedures to control the line of duty with the VHDL code, the compiler error-free!
PushButton_Debouncer
- KEY INPUT DEBUNCE VERILOG-KEY INPUT DEBUNCE verilog
1
- 加法器的VHDL代码，可以在很多地方直接应用
pt
- FPGA display red,blue and green color
m_divider_int
- 14bit pipeline 除法器，在Xilinx V5上可以跑到100M，输出延时3cycles-14bit 100M pipeling divider