资源列表
testUSART
- 将一块板的发送并口转为串口，完成两块板的通信-Will the board parallel port to send a serial port, complete two boards communications
AHB
- 比较好的Verilog实现的AHB master。-Better AHB Verilog realization of the master.
miaobiao
- 用硬件描述语言Verilog HDL完成秒表设计模块，使用数码管。-Using hardware descr iption language Verilog HDL to complete the stopwatch design module, using digital tube.
seg_example
- DE2-115 seg example source code
lcdexample
- cpld实现与液晶屏并口通信，VHDL 语言编程。对VHDL初学者应该有帮助的。-cpld achieve parallel with the LCD screen communications, VHDL programming. Right VHDL beginners should help.
ma
- 基代码发生器的原代码，供大家学习研究，共同探讨
mytaxi
- 本出租车计费器要实现的功能是出租车按行驶里程收费，起步费为7.0元，行驶3公里后再按2元/公里计费，车停时不计费。能预置起步费和每公里收费，并能模拟汽车启动、停止、车速等状态。
ahb_master1
- this is a code of AMBA AHB master protocol in verilog
VHDL-test-code-Timing-Components
- VHDL实验代码：时序部件实验-启停电路，这是一个基于VHDL开发的程序，非常的实用-VHDL test code: Timing Components experiment- start-stop circuit, a VHDL-based development process, a very practical
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
ps2_rx
- 在VHDL里实现的ps2 键盘接口的接收端功能-Implemented in VHDL in the ps2 keyboard interface of the receiver functions
ahb_master1
- AHB master 关于ahb总线协议中的master的encode -AHB master