资源列表
frm_sync
- 此程序为帧同步程序，采用状态机的VHDL描述方式编写。-This procedure for frame synchronization procedures, using the state machine to prepare the way VHDL descr iption.
lcd
- 基于fpga的lcd显示模块vhdl描述，只需修改相关参数即可使用-Fpga based on the lcd display module vhdl descr iption, simply modify the relevant parameters to use
clock
- 基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock
USBhpi
- USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0\FPGA代码(Quartus)-USB FX2LP TO TI5402 HPI PORT MODE BOOT V1.0 \ FPGA code (Quartus)
fifo_ctrl
- fifoctr 寄存器控制 verilog代码-FIFO ctr
multier
- 流水线高速并行乘法器，流水线设计，并行加法计算-High-speed parallel pipelined multiplier
Simple_Verilog_Code_For_Beginner
- verilog code for beginner (adder, comparator, mux, or, and subtractor)
DMAC
- 该程序实现在ALTERA FPGA 上搭建NIOS系统，实现DMA 传输-The program built on the ALTERA FPGA NIOS system, DMA transfer
jishuxianshi
- 用VHDL语言，实现计数显示电路的设计。-Using VHDL language, counter display circuit design.
VGA.txt
- 基于FPGA的VGA显示器彩条发生器 是必备的VGA原码控制
clock
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
DPRM
- a simple ram using vhdl platform provides to create a fine ram mamory .