资源列表
VHDL_ReversibleCounter
- 可逆计数器(两位十六进制,以十进制方式显示即从00,01数到14,15然后00,01再到根据10hz晶振(低频都可选,视板子情况而定)作为时间脉冲计数,rst键可以重置(清零 )计数器,drct键选择加法计数还是减法计数.-2-bit-Hexadecimal Reversible Counter(decimal display)
interleaver
- interleaver for wi max phy
vga_pattern
- Program to create a pattern on VGA monitor
yiweijicunqi
- 移位寄存器实现串并转换，8位移位寄存器，具有一步复位，同步置数，同步清零-Serial shift register implementation and conversion, 8-bit shift register, with a further reduction, the number of synchronous set, synchronous clear
chufa
- 用VHDL设计的四位除法器，可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
hello_world
- speed fan control,风扇速度的控制，基于 FPGA，用C 语言编程-speed fan control embedded system
spi_mcu
- SPI Slave接口，实现与外部控制器的接口。实现外部SPI口到逻辑内部寄存器模块接口的转换-SPI Slave interface, interface with external controller. SPI port to achieve external conversion logic module interface internal registers
sy9
- 交通灯 VHDL 程序，程序功能：红灯绿灯各9秒，黄灯3秒-Traffic lights VHDL program, the program features: 9 seconds of red light and green light, 3 seconds of yellow light
vhdlcode
- VHDL code in ISE (for collecting the ADC samples from kit and for viewing final output)
Verilog_uart
- UART communication code
streamline_divider
- streamline 除法器，是国外一个工程师所写,verilog语言，modelsim测试-streamline divider
led
- 基于xc4vsx25芯片的verilog语言程序，用于实现流水灯功能，包含源程序代码及管脚设置文件，本程序均通过调试，可于SEED-XDTK_V4实验箱上实现。-Verilog language program based on xc4vsx25 chips for light water features, including source code and pin settings file, the proceedings were conducted by debugging can b