资源列表
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
four_adder
- 通过调用被实例化的模块来实现四位全加器功能-Four full adder function is achieved by calling the module is instantiated
MessureDistance
- 使用HC-SR04超声波测量距离IP，精确度达1mm，最远4m程序有详细的注释。-Use HC-SR04 ultrasonic distance measuring IP, an accuracy of 1mm, the farthest 4m procedures detailed notes.
lcd1602
- FPGA VHDL LCD1602驱动，已验证-FPGA VHDL LCD1602 driver, verified
verilog
- 一个简单状态机的.v文件，含testbench
srbjq
- vhdl实现的三人表决器，大家一起交流一下，-VHDL realization of three voting machines and we can work together to exchange about
clock
- verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
PPM_Coder
- PPM 编码器 按照PPM编码格式编写的普通VHDL代码-PPM PPM encoder encoding format prepared in accordance with the ordinary VHDL code
sRAM
- FPGA与Sram通信并液晶显示，程序为verilog语言-FPGA and Sram communication and LCD, the program for the verilog language
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
UART_Rcvr
- uart 的源程序，用verilog编写-uart