资源列表
DISPLAY-vhdl
- vhdl描述的显示代码 maxplus2开发环境-VHDL descr iption of the display code development environment maxplus2
UltraEdit_shown_VHDL_keyword
- 让UltraEdit显示出VHDL的语法关键字-Let UltraEdit syntax shown VHDL keyword
chufaqi
- 64位除法器，可计算商和余数，时序，测试通过-64bit divider
xor8
- verilog hdl 基础域运算加法的仿真综合实现-verilog hdl xor8
CPU
- 基于VHDL语言的简单CPU，实现简单的加、减、乘-VHDL language based on the simple CPU, to achieve a simple addition, subtraction, multiplication
AD_RW
- AD1555/1556联合采样程序，可自行设置采样率，经检验可用。-Joint sampling program in AD1555/1556 to set the sampling rate, the test can be used.
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
ads7883
- FPGA中用Verilog HDL语言读取串行ads7883数据-FPGA using Verilog HDL language to read the serial data ads7883
TSTBENCH
- FFT implementations using fused floating point operations
endat_c
- 用于读取海德汉绝对位置编码器的位置数据。ENDAT2.1接口-Read the data from ENDAT2.1
vgav2
- fpga vga 输出，60HZ 640*480 8位灰度图像 采用verilog语言编写-fpga 640*480 60HZ vga output，writed in verilog
fir
- 用verilog编写的fir滤波器程序,可实现fir的硬件综合-Fir filters using verilog written procedures