资源列表
RTPPayloadFormatforReedSolomon
- ReedSolomon FEC used in RTP
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
Mux41a
- Basys3 4选一数据选择器代码，初级者学习，在板子上试验过，没问题。(Basys3 4 select a data selector code)
Transmit_subsystem-master
- 千兆以太网的相关资料，包括相关的一些测试文件(Gigabit Ethernet related information)
ledrun
- 基本的流水灯程序，4灯循环，verilog(Basic flow lamp program)
08_ethernet_1g
- Artix7 XC7A100T芯片控制千兆PHY的二层通信，源代码(Artix7 XC7A100T chip control Gigabit PHY two layer communication, source code)
09_ethernet_100
- Artix7 XC7A100T芯片控制百兆PHY的二层通信，源代码(Two layer communication Artix7 XC7A100T chip control PHY megabytes, source code)
Adept SDKv1-3
- 开发板资料，适用于赛灵思的板子，欢迎大家下载(Examine your code to determine if this port should be declared as an INOUT, or if the assignment to this port should not have been made. If this signal connects to submodules, consider the type and lower-level functionality of
spi_master
- 用Verilog写的SPI代码，可读可写，刚仿真完，还没上板，尴尬，主要是官方限制不上传就不能下载～～～～～～～～～～～～～～ 下面的英文是百度翻译过来的，鬼畜的我都不知道啥意思～～～～(The SPI code written in Verilog is readable and writable. After the simulation is finished, it is not yet on board. Awkwardly, it is mainly that official r
VHDL简易电子琴设计(1).doc
- 这是一个简单的基于vhdl的电子琴，有自动播放和使用按键来制作不同的音色。(The design of a simple electronic organ based on VHDL, with the automatic playing and the use of keystrokes to make different tones)
exp_fft_test_724
- 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data
Assignment-1.3.tar
- verilog codes for different basic digital circuits elements