资源列表
Assignment-2.1.tar
- verilog codes for different basic digital circuits elements new
Assignment-2.2.tar
- verilog-HDL codes for different basic digital circuits elements
Assignment-2.3.tar
- HDL code using verilog
Q1.tar
- implementation of basic elecronics components using verilog HDL
Q2.tar
- vereilog design files for beginer
Q3.tar
- hdl using verilog lenguage
Q4-a.tar
- verilog coding beginer level
Q4-b.tar
- beginer level verilog coding
Q22-c.tar
- hdl design using verilog for beginer
uart_txd
- 用VHDL实现的串口数据发送模块。使用的软件为ISE和modelsim。(Serial data transmission module implemented with VHDL.The software used is ISE and modelsim.)
project_PmodMic_PmodAMP2_1
- 用digilent公司的basys3开发板，外接Pmodmic和PmodAMP2模块，实现对声音的采集和复原。程序基于VIVADO 2015.4，附带例化的低通滤波器。实际可用。(Use digisen's basys3 development board, external Pmodmic and PmodAMP2 modules to achieve sound collection and recovery. The program is based on VIVADO 2015.4 wi
project_PmodKYPD
- 用Digilent公司BASYS3开发板和PmodKYPD模块，实现对按键的检测。程序基于VIVADO 2015.4，语言为verilog。(Digilent's BASYS3 development board and PmodKYPD module are used to detect keystrokes. The program is based on VIVADO 2015.4 and the language is verilog.)