资源列表
alu
- Code to synthesize Arithmetic Logic Unit
ActelFPGA
- ACTEL FPGA system is introduced, the older the FPGA
SystemVerilog_Synopsys
- systemverilog introduction by synopsys
verilab_dvcon2012_uvm_cooper
- Getting Started with UVM by Verilab
PPM
- 对4比特二进制数据进行PPM调制，位宽可修改(PPM modulation for 4 bit binary data)
DVCon_Europe_2015_T01_Presentation
- Advanced UVM Tutorial by Verilab
mj10
- 实现门禁系统，可以做网店实战的项目，对接数据库，不过里面没有数据库想对应的测试数据(The implementation of the entrance guard system, can do online shop actual projects, docking database, but there is no database to corresponding test data in it.)
and_gate
- ALU设计与开发，四位的，简单可仿真，内部里面有text班车(ALU design and development, four bit, simple and emulation)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
Multi_cpu
- 多周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
Up_Down_Counter v1.0
- FPGA Up/Down couner Module
RGMII_RECEIVER
- This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.