资源列表
Led_Contrast
- this source code is used for dimming the light intensity from LED witht fpga
1
- 基于VHDL的三层电梯控制器-VHDL-based three-story elevator controller
Power_Supply_Monitor
- This module implements the logic for monitoring power supply inputs
display
- vhdl实现的显示模块的源代码，是电子竞赛的必备源码-VHDL realization of the display module s source code, is an essential source of electronic competition
shifter
- 完成一个加速器设计，全加器，具 8位计数器-Complete a accelerator design, full adder, an 8-bit counter
ywjc
- 采用状态机的方法实现移位寄存器，用Verilog HDL编写，已经通过验证。-The method uses the state machine implementation shift register, with write Verilog HDL has been verified.
fsm_moore_1_always
- 使用1个always块描述Moore FSM（摩尔状态机）-Moore FSM 1 always
fpga_com_intf
- 一个简单的串口通信程序，verilog, 很容易实现，而且占资源很少-a simple serial interface
atel2_bin
- 串行口 VHDL 嵌入式 单片机 串行接口实现-serial port
c5c
- 实现5人表决的功能，并有倒计时跟指示功能。-Implement 5 people vote, and the timing and voting results show.
wanyongbiao
- EDA的课程设计，可以实现带有两位分和两位秒的四位数码表显示-EDA curriculum design can be achieved with two minutes and two seconds, four digital table shows
mult_16
- 用verilog实现对三个16位数进行相加乘法器-Three 16-digit sum of the multiplier Verilog