资源列表
2016sell
- 此售货机模块包括：投币处理模块，商品选择模块，投币模块，分频模块，控制器模块，计时模块，LED灯显示模块，找零模块，出货模块，-The vending desktop module includes: coin processing module, product selection module, coin module, frequency division module, controller module, timing module, the LED display module, t
project_wave
- 波形发生器，生成三角波和正弦波,功能较为简单，可以通过改变频率控制字来改变输出波形状态-Waveform generator to generate triangular wave and sine wave
mux_16bit_sign
- 16位有符号和无符号乘法器FPGA源代码-16-bit signed and unsigned multiplier FPGA source code
ADP5052.PDF
- 多路稳压输出，可配置个电压，非常适合用于fpga电源-Multiple regulated output voltage can be configured very suitable for fpga power
AD9826-verilog
- 使用Verilog编写的ad9826的控制模块-the module of ad9826 with verilog
baseonFPGAclock
- 用verilogHDL语言写的基于FPGA的电子钟。里面包含闹钟、秒表、日历、时间设置等功能，可用LCD显示-verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD
Altera DE2 TV BOX with Effects Project
- Altera DE2 TV BOX with Effects Project maintaied for Cyclone 2
bcd_add_1bit
- 二进制码到BCD码的转换 1位BCD加法器 2位BCD加法器-BCD code to binary code conversion of a BCD adder two BCD adder
char_7seg
- 七段数码管显示 显示简单字符 显示0～9数字 循环显示4个字符 -Seven-segment LED display simple characters, 0-9 digital loop display four characters
mux_2to1
- 2选1的数据选择器 即当s＝1时，输出m＝y；当s＝0时，输出m＝x。 -Data selector 2-to-1 that is, when x = 1, the output m = y when s = 0, the output m = x.
rom_255
- 入通过键盘控制或者通过50MHz晶振分频后以每1秒步长发生变化，通过8位并口输出数字信号，并将该数字信号经过译码电路后用七段数码管提示输出信息。-By controlling the keyboard or by 50MHz crystal occur long after the division to change every second step, through the 8-bit parallel digital output signal, and the digital sign
traffic_lights
- 运用Verilog HDL编程语言，实现十字路口的交通灯功能，可在FPGA等硬件上进行仿真（默认硬件晶振为50MHz）。-Using Verilog HDL programming language, to achieve the crossroads of traffic lights function, can be simulated in FPGA hardware on (the default hardware crystal is 50MHz).