- ConvertEMFToBMP_demo 将图形文件的格式从EMF转换为BMF的工具
- Classic_php_code_management_system_development_and php开发设计管理系统经典代码Classic php code management system development and design
- iso-SE-Template 详细的软件工程开发过程指导规范
- The-three-layer-architecture 把ADO.NET用三层架构来显示
- antenna 采用matlab仿真了天线罩的随着入射波的角度变化的反射系数的变化
- piusen_v35 最大似然（ML）准则和最大后验概率（MAP）准则
资源列表
Pmod_tr2
- FPGA pomd 接口演示实验包括蓝牙，gps，液晶显示等-FPGA pomd demonstration experiments interfaces including Bluetooth, gps, LCD, etc.
project_1
- 使用fpga实现mips处理器代码verilog-Use Code verilog fpga realize mips processor
sin_generator
- 基于QUARTUS ii的ROM的正弦方波锯齿信号发生器。-Sine square, wave saw and tooth signal generator based on ROM of QUARTUS II.
RGB2Y_lattice
- 这是基于lattice fpga数据转换的一个模块，将rgb888转成标准的yuv中的亮度y。整个工程在diamond2.0版本下编译运行。-This is based on a modular lattice fpga data conversion, it will turn into a standard rgb888 yuv luminance y. The whole project is compiled to run under diamond2.0 version.
Intel8080_lattice
- 基于lattice fpga芯片的intel8080总线模块，简单易懂，适合初学者。这个工程在diamond2.0版本编译运行。-Based lattice fpga chip intel8080 bus module, easy to understand for beginners. The project runs diamond2.0 version of the compiler.
spi_slave_lattice
- 这是基于lattice fpga 做的spi slave模块。简单易懂，适合初学者。代码使用状态机描述。整个工程在diamond2.0版本编译运行。-This is based on lattice fpga do spi slave module. Easy to understand for beginners. The code using a state machine descr iption. The whole project is run diamond2.0 version o
Lvds_lattice
- 这是基于lattice fpga 芯片的 ttl 24bits（rgb888）模块。简单易懂，修改输出分辨率只需要修改几行宏定义。整个工程文件在diamond2.0版本上编译运行。-This is based on ttl 24bits lattice fpga chip (rgb888) module. Easy to understand and modify the output resolution is only need to change a few lines of macro
Key_Filter
- 用Verilog 语言写的 按键消除抖动程序-Verilog language used to write programs eliminate jitter button
XC3S400TQ144
- Just little program for xilinx FPGA. It is can be used as a example for education.
time_test
- 利用10M的时钟，设计一个单周期形状的周期波形。这是用Verilog写的-Use 10M clock cycle design a single cycle waveform shape. This is written in Verilog
Serial_Adder
- 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder
my_alu
- 一个简单的ALU程序设计，实现以下功能： 逻辑运算：与、或、非、异或、逻辑左移、逻辑右移 算术运算：加、减 -A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction