资源列表
diviseurFrquence50MhzTo1hz
- this file about frequency divider 50 MHz to 1 Hz used in 7-segment display
m_counter
- this project about compteur m bit compiled and implanted in cart fpga xilinx 3E, with file .HDL and .bit
MUX4_1_2bits_fonction
- this project about multiplexer four to one compiled and implanted in cart fpga xilinx 3E, with file .bit
DEMUX1_4
- this project about demultiplexer one to four compiled and implanted in cart fpga xilinx 3E, with file .bit
Multiplier
- 设计一个能进行两个十进制数相乘的乘法器，乘数和被乘数均小于100。-Can design a multiplier multiplying two decimal numbers, the multiplier and multiplicand are less than 100.
Simple-design-of-traffic-lights
- 交通灯的显示有很多方式，如十字路口、丁字路口等，而对于同一个路口又有很多不同的显示要求，比如十字路口，车子如果只要东西和南北方向通行就很简单，而如果车子可以左右转弯的通行就比较复杂，本实验仅针对最简单的南北和东西直行的情况。-Traffic lights show there are many ways, such as intersections, T-junction, etc., and for the same intersection there are a lot of differ
ARM(Verilog-a-VHDL)
- 基于VHDL/Verilog实现的arm0,ARM5-7核-Based on VHDL/Verilog implementations arm0, ARM5-7 nuclear
FPGA-2048
- 一开始方格内会随机出现2这个小数字，每次可以选择上下左右其中一个方向去滑动，每滑动一次，所有的数字方块都会往滑动的方向靠拢外，系统也会在空白的地方乱数出现一个数字2或4方块，出现2的概率是出现4的概率的3倍，相同数字的方块在靠拢、相撞时会相加。系统给予的数字方块不是2就是4，玩家要想办法在这小小的16格范围中凑出“2048”这个数字方块。断的叠加最终拼凑出2048这个数字就算成功通关。当所有16格数字已满，无法叠加，且没有出现2048这个数字则算游戏失败。-Will randomly appea
EPD
- Quartus II开发环境下的鉴相器的图形实现。-Quartus II phase discriminator
cronometro1.c
- cronometro atmel 328p code vision avr
Divisor_Frec
- Code in vhdl of divisor of frequency in FPGA
timecounter60sandpause
- 计时器数码管做到60s计数，外接键盘按键暂停-Digital timer 60s do count, an external keyboard to pause