资源列表
FloatALU
- 用Verilog HDL实现的IEEE754浮点数加减乘除法器-float number alu
paomadeng
- 这是一个跑马灯项目，语言为verilog，basys3开发版开发。-this is a project about paomadeng.
spartan3E-seg-driver
- spartan3E seg display driver-spartan 32 seg display driver
fadder4
- 例化语句生成的四位全加器代码，写在word里了，也有MODELSIM测试代码-Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code
PPPdecoder
- decoder in vhdl A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders because they are simpler to design.
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
7-16
- CIC滤波器的VERILOG HDL语言实现，通过QUARTUSII软件编译通过，仿真结果是正确的
VHDL测频率周期
- 用VHDL语言编写的频率计程序，用来测量方波的频率以及周期。
uart
- verilog 编写的FPGA串口报文收发程序，带奇偶校验位，并含有DS18B20温度传感器驱动程序，可以自行设置波特率.-verilog prepared by the FPGA serial transceiver procedures packets with parity, and contains a temperature sensor DS18B20 driver, you can set the baud rate yourself.
full_adder
- 用verilog语言编写的全加器模块代码，在ISE软件环境下编译开发，希望对大家有所帮助！-With verilog language full adder module code in ISE software compiler development environment, we want to help!
CPU_single-(2)
- 单周期CPU设计源码，基于Quatus II，亲测可用-Single-cycle CPU design source code, based on Quatus II, pro-test available
32-bit-carry-look-ahead-adder
- This file contains Verilog codes