资源列表
fpu_arch
- Floating point architecture
FLOAT
- Floating point vhdl coding
mulfp
- Mulfp for vhdl coddin-Mulfp for vhdl coddingg
post_norm_fmul2
- Post_norm_fmul2 vhdl code
fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
eluosi_game
- 使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use
24Bit_Spi
- 24位数据转化为SPI指令，注释详细，位宽可自行更改，适用于多位数据转化为串行数据，实测可用-For SPI instructions, detailed notes, bit width can be self change, applicable to a number of data conversion for the serial data can be measured 24 bit data transformation
LcdCtrl
- FPGA控制12864液晶屏，16位总线实现数据及指令发送，配合SPI模块可控制SPI型液晶屏，程序中包含液晶的初始化指令，实际使用过-FPGA control 12864 LCD screen, 16-bit bus for transmitting data and instructions, with the SPI module can control SPI LCD screen, LCD initialization instruction program contains, act
fangbo
- 将运动控制卡的方向信号与脉冲信号转换为两路正交方波信号信号（模拟光栅信号）-The direction of the signal and the pulse signal is converted motion control card for two orthogonal square wave signal signal (analog signal raster)
count_5
- 5路光栅信号的数字滤波、四倍频、同步锁存、计数-5-way digital filtering raster signal, quadrupled synchronous latch count
New-WinRAR-archive.RAR
- 250NM CMOS TSMC MOSIS PARAMETERS
cp_model
- 原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用 -Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench