资源列表
oc_i2c_master.rar
- 这是一个I2C的IP。直接拷到altera公司的相应软件的目录下，即可应用。,This is an I2C of IP. Kaodao altera directly corresponding software company directory, can be applied.
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
pipeline.rar
- 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧,About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Max_PlusII_ppt.rar
- Max+Plus II 的ppt文档，看后可以很轻易上手Max+Plus II,Help
usart.rar
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order. ,USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
vga_display.rar
- VGA controller源码及显示汉字和ascii字符的c代码实例，已在DE2-70上实现,vga_controller source code and c code which can display chinese charactors and ASCII code on the VGA
OpenSPARC_DDR2_controller_RTL_
- 基于FPGA的DDR2控制程序，用verilog编写的。,FPGA-based DDR2 control procedures, prepared by using Verilog.
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
single_clock_divider.rar
- 单周期除法器，速度快，满足频率要求，使得单周期内得到除数,Single-cycle divider speed, to meet the frequency requirements
DE2_TV.rar
- 在altera公司的ED2板子上实现视频功能，这是完整的视频工程！,ED2 at altera board on the company' s implementation of video features, this is a complete video works!
ISA.rar
- pc104代码，这是本人调通过的。标准ISA通信接口，用VHDL编写,pc104 code, This is my tune adopted. ISA standard communication interface, using VHDL prepared