资源列表
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
Altera_8051_IPcore_v1.2.rar
- Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5
parallel_to_serial.rar
- 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
Quartus9.0crackfile.rar
- 这是最新版的Quartus9.的破解文件，怎么做我就不说了，里面说的很清楚，我已经尝试，保证能用！希望大家学习愉快！,This is the latest version of Quartus9.' s Crack file, how do I do not say, which says very clearly, I have tried to ensure that can be! Hope that we learn with pleasure!
modulation.rar
- verilogHDL编写的QPSK选相法调制模块，在ISE软件中仿真过，可综合，绝对是正确的,verilogHDL preparation phase of the QPSK modulation selection module, in the ISE simulation software that can be integrated, is absolutely correct
shuzi.rar
- 数字电子钟设计，整点报时，时分秒分模块设计，另附实验报告和实验结果，内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
SD_card_src.rar
- 一个基于VHDL语言的8位SD卡读取程序。含有源代码和说明,VHDL language based on an 8-bit SD card reader. Containing the source code and descr iption
FPGA_nCLK.rar
- VHDL语言的高频时钟分频模块。一种新的分频器实现方法。,VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
lcd_controler.rar
- 用FPGA设计12832中文液晶控制器,采用状态机的方式，提高稳定性！,FPGA cyclone control 12832LCD
CPLD_frequency_divider.rar
- 这是CPLD原始代码程序，是天祥电子所写，希望大家会喜欢！,This is the original code CPLD program is written by Tienhsiang e hope you will like it!
LCD.rar
- LCD Interface_Xilinx.CPLD源码参考设计,LCD Interface Xilinx CPLD
squareroot.rar
- vhdl源代码,可以开16比特的平方根，算法简单，速度快,this is a vhdl code for square root