资源列表
USB_send_recive
- 完全用verliog写的FPGA和CH372与电脑USB设备通信。可以和电脑收发数据，已经测试成功，如有疑问留言，程序可能有点乱，-Written entirely in verilog FPGA and CH372 USB devices to communicate with the computer. And computers can send and receive data, it has been tested successfully, if in doubt leave a m
Least_Squares
- 基于FPGA两种基于非线性最小二乘法的电力系统频率跟踪方法，搜索算法和Levenberg-Marquardt算法。- least square method FPGA
HDMI_test
- 基于Xilinx的FPGA的spartan3的HDMI测试功能刷屏显示。-Based on Xilinx s FPGA spartan 3e of the HDMI display refresh function tests.
DFlipflop
- Verilog Program for a d flipflop
Counter
- Verilog program for a counter
Comparator
- Verilog program for an 8bit up down counter
ClockGenerator
- Verilog code for a programmable clock generator
Adder_4bit
- Verilog Program for a 4bit Adder
serial_r
- 串口通信的接收代码，适合工程应用，也适合入门学习，个人调试无问题-Receive Code serial communication, for engineering applications, but also for learning portal, individual debug no problem
OFDM-Verilog
- 基于FPGA的OFDM的实现，Verilog语言。-OFDM based on FPGA,by Verilog
AX301
- 黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301-Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output