资源列表
bixiang
- 程序的主要功能是实现两个波形的相位比较，并把输方波。-The main function of the program is to achieve the phase comparison of the two waveforms, and the transmission of the square wave.
ad-kongzhi
- 主要用于ad的控制，包括时钟的设置和输出地址的控制。-Mainly used for the control of AD, including the clock settings and the output address of the control.
fenpin
- 输出比设定的时钟频率小8倍的时钟，实现分频功能，可用于芯片控制。-Output than the set of 8 times the clock frequency of the clock, to achieve frequency division function, can be used for chip control.
float_add_module
- verilog编写的32位浮点数加法器。Start_Sig 和Done_Sig 是控制信号，作为启动和反馈完成，A 和B 是32 位宽的操作数输入信号，Result 则是32 位宽的输出结果。-32bits float add module use Verilog HDL.
liushui
- 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
fifo
- 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
shuma
- 本程序使用xilinx芯片，verilog编写，实现数码管功能，数码管为共阳极数码管，您可变换UFC管脚定义适应自己的开发板-This program uses xilinx chip, verilog written realize digital functions, digital control for the common anode digital tube, you can transform the UFC pin definitions to adapt their own d
zhuangtai
- 本程序实现了报文功能，在通信传输中经常会用到，使用芯片为xilinx，verilog语言编写-This program implements packets, in the communication transmission is often used, the use of chip xilinx, verilog language
vga2
- 本功能主要实现了VGA的显示，分辨率为1024*768，包内有制作好的coe文件存入rom，适合xilinx芯片-This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
basys3_timing
- 基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL-Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL
vga_test
- 分辨率可调的vga源码，用vivado的平台，完整的工程-Adjustable VGA resolution source code, using vivado platform, a complete project
OQAM_PREPRO
- OQAM modulation VHDL code