资源列表
DS18B20
- DS20B18温度采集模块（一线式总线读取）-DS20B18 temperature acquisition module (bus line read)
1602timer
- 用verilog实现的，在1602液晶显示万年历修改FPGA芯片类型可以直接使用-Using Verilog to achieve, in the 1602 liquid crystal display calendar modified type of FPGA chip can be used directly
verilog-HDL
- 蜂鸣器的FPGA设计，verilog语言，工程文件全-Buzzer FPGA-based design
PS2_VGA
- VGA controller for new designer. tested ok. spartan3an board .
VHDL-FPGA-xilinx-altera-frily
- VHDL的经典经验。相当的不错，一个多年开发FPGA的工程师自己的记录，适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
CD1_PHOTO_ABLUM_1920
- FPGA nios 的摄像头 1920像素程序-FPGA nios cameras 1920 pixels
Quartus-II
- Altera® Quartus® II 设计软件是用于可编程片上系统 (SOPC) 的最全面的设 计环境。-Altera ® Quartus ® II design software is used for system-on-programmable chip (SOPC) the most comprehensive design environment.
my_uart_top
- UART串口传输，参考别人写的，大家修改下就可以用，欢迎参考。-UART serial communication
CD1_PHOTO_ABLUM_1920
- 使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存-Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
DE2_Default
- DE2开发板基本代码 DE2开发板基本代码 -basic
counter.rar
- 初学者学习modelsim的好例子，基于Verilog的计数器，带测试源码，在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.