资源列表
AD_9215
- 用Verilog实现AD9215驱动的开发-AD9215 with Verilog-driven development to achieve
ps2_fpga
- 键盘输入，在数码管显示对应按键的编码，从中了解键盘输入原理-Keyboard input, the digital display corresponds to the encoding keys
counter_0-to-9999
- 数码管计数，在数码管上计数，从0计到-Digital counting experiment, the digital count on, count from 0 to 9999
Learn-FPGA-through-example
- 深入浅出玩转FPGA(大量例程和PDF教程)-Learn FPGA through example
DF2C8_12_DS1302
- verilog实现DS1302时钟控制,程序已验证没有问题 -verilog achieve DS1302 clock control procedures have been verified there is no problem
nnARM01_11_1_3
- 包含详细的源代码，可以稍加修改就能应用在您的设计中-Contains detailed source code can be modified can be used in your design
Taxi-automatic
- 本项目实现一个出租车自动计费器。计费包括起步价、行车里程计费、等待时间计费三部分，用四位数码管显示总金额，最大值为999.9元。起步价为5.0元，3公里之内按起步价计费，超过3公里，每公里增加1元，等待时间单价为每1分钟0.1元。用两位数码管显示总里程，最大值为99公里，用两位数码管显示等待时间，最大值为99分钟。-The project achieved a taxi meter automatically. Billing, including starting, mileage charg
fifo_ex4
- 深入浅出玩转FPGA代码 实验四FIFO模块 基于EP1C3-Layman Fun FPGA code EP1C3 based experimental four FIFO modules
bsconvert
- 基于FPGA的实现数据串并转换的程序，可以把8位串行数据转换为8位并行数据，或把8位并行数据转换为8位串行数据等-FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
multifunction_clk
- 多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证-Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation
List.3DS-Proteus-ARES
- 3D Model to Proteus/ARES 3D PCB Visualization
divfreq
- 除頻器，用於數位電子乙級考試的時候，將主板上4MHZ的訊號進行除頻的硬體描述語言-Div Freq