资源列表
timing_controller
- 本程序为船舶导航雷达时序控制模块的整个系统，包含QPF工程。-The program for the entire ship navigation radar system timing control module contains the QPF project.
ml605_PCIe_Gen1_x8_rdf0008_13.2_c
- 基于ML605开发板生成的x8 PCIE验证程序，可在ISE 13.2上正常运行，用户可根据自身需求进行修改-ML605 development board based on the generated x8 PCIE verification process can be run properly in ISE 13.2, the user can modify according to their needs
SDRAM_verilog@tequan
- 本资源是特权同学编写的sdram控制器，包括数据读写，串口输出，很有学习价值-This resource is privileged students write sdram controller, including data read and write, serial port output, is worth learning
reg4b
- 这里有12各源代码，是我自己写的，希望对大家有所帮助-Here are 12 of the source code, I wrote it myself, and I hope to be helpful
ImageDivision
- 基于SystemGenerator的图像分割，成功在XilinxFPGA上验证，附带网表。-Based on the image segmentation SystemGenerator, success on the XilinxFPGA verified with the netlist.
04-vga_module_pic_color
- vga程序 verilog语言编写 共五个模块 这是第四部分-vga verilog language program which is part of the fourth of five modules
spi final
- verilog 实现spi 串口 通过FPGA板可以看出数据传输(verilog spi can be demonstrated with FPGA)
CycloneIII_EP3C40F780C8_2_Hello
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,hello 实验代码-SOPC,CycloneIII，EP3C40F780C8，hello code
pld-tutorial
- pld的实践教程，完整详细的讲解适用于初学者以及研究开发人员-pld hands-on tutorials, full and detailed explanation for beginners as well as research and development staff
TAXI
- VHDL硬件描述语言实现出租车计费器的功能，不同时段，不同行驶状态费用可以调节-VHDL hardware descr iption language taxi meter' s functions, different times, different running state fee can be adjusted
SPARTEN-3E-development-board-course
- SPARTEN 3E 实验指导书，语言是VHDL-The experiment instructions of SPARTEN 3E, language VHDL