资源列表
ml605_PCIe_Gen1_x8_rdf0008_13.1_c
- ML605_Reference_Designs:ml605_PCIe_Gen2_x4_rdf0009,xilinx开发板的PCIe设计例程，包括源码和下载文件.verilog-ML605_Reference_Designs：PCIe codes and download files include ace and bit file
oled
- 驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)
v2
- rs422串口指令控制以及AD7824芯片的数据采集-rs422 serial control timing
DE2_CCD_PIP
- 实现DE2上的摄像头采集，实现画中画，利用两个摄像头，在VGA上实现两个画面同时出现-DE2 on the camera to achieve the collection, to achieve PIP, using two cameras, the VGA screen to achieve two concurrent
Circuit-Design-With-VHD
- Circuit Design With VHD
fir
- fir 滤波器的程序文件和测试文件，仿真数据和matlab仿真数据进行过比对，matlab采用fdatool生成的低通滤波器，采样率为24兆，通带2.5M，截止频率为5M(FIR filter program files and test files, simulation data and MATLAB simulation data have been compared, Matlab using FDATool generated low-pass filter, sampling rat
ex15
- vhd数码管测试源码，同时六个数码管控制，显示。-using ALTERA s FPGA design, QUARTUS software development platform.
dds
- the fir filter for digital design synthesizer-the fir filter for digital design synthesizer
verilog实现FSK
- 用verilog语言，采用DDS技术实现的FSK
Prototyping-of-Digital-Systems---Hamblen-a-Furman
- Prototyping of Digital Systems - Hamblen & Furman
22_sos_system
- 这个是我从黑金社区上找过来的 是关于sos系统设计的代码 希望对大家学习FPGA有用-This is I can come the black community is on the SOS system design code, we hope to learn useful FPGA
uart
- 基于verilog的fpga串口通信,rx,tx.两根线(Basend on verilog fpga uart tong xin)