资源列表
COUNT_4qiduan
- VHDL源代码.设计一个模为4的计数器，并在实验箱上用七段数码管显示结果-VHDL source code. Design a scale of four counters, and the experimental box used in paragraph 107 of Digital Display Results
16latch
- 16位锁存器，此程序通过quartusII软件调试通过
8255int
- 8259芯片中断控制LED 扳动SP按钮 LED点亮或熄灭-8259 Interrupt Control LED flip-chip LED lit or extinguished SP button
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
filer_pipeline
- 基于流水线的滤波器的设计与实现，verilog代码，xilinx，ISE，-Based on the assembly line of the design and realization of the filter, verilog code, xilinx, ISE,
square
- This a verilog code for the generation of a square wave-This is a verilog code for the generation of a square wave..
l2
- write the verilog code for the following specification & perform the linting checks
AD-DA_VHDL
- 用VHDL编程实现FPGA对的AD9201控制-FPGA using with VHDL programming to control the AD9201
shifter
- 左移门，在vhdl环境下实现左移-Left to move the door
BC-DATA
- B61580 1553B BC模式配置数据-B61580 1553B BC data
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
addersubtractor9
- vhdl code for adder 8bit