资源列表
fifo_sync
- 脉冲同步电路,简单修改就可以使用,很使用的.
interleaver
- 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
ArithmeticCoding
- this is use for 8-bit ALU
USB_SLAVE_700AN
- 基于verilog的USB2.0同步写操作代码-usb2.0syn write code
mm1
- 基于随机数组中的最大值与最小值的选择器，可自由设定输出时钟和数组大小-Maximum and Minimum Value Selector
TXD
- TxD - simple RS232 transmitter
myfir
- fir滤波器的源代码 基于乘法器结构的线性相位滤波器-The source code for fir filter structures based on linear phase filter multiplier
second
- 0-99秒表数码管显示，有停止，启动功能-0-99 stopwatch digital display, a stop-start function
testad
- 此模块是FPGA系统中的指示模块，可分别指示系统的正常工作，程序烧写，工作模式，等状态，控制5个LED的状态来达到指示系统工作的目的-This module is the instructions in the FPGA system module, can the normal work of the indicator system respectively, burn written procedures, work patterns, such as state, control the
counter_decrement
- counter which counts from 15 to 0,15 to 1 ,15 to 2 similarly till 15 to 15
Proj
- verilog/vhdl 串行口232通信程序-Spartan3E开发板调试通过-verilog/vhdl serial port communication program-Spartan3E 232 development board debugging