资源列表
VHDL
- 再FPGA上經由VGA顯示一半黑一半白的圖示-By the FPGA and then VGA display half black half white icon
multi8
- 8位乘法器-multi8
trafficlight
- traffic light controller vhdl program
sp
- vhdl code to change bits stream from serial to parallel
sequence_dectect
- sequence_dect 实现6个状态，即6种选择的状态机。状态机的一个极度确切的描述是它是一个有向图形，由一组节点和一组相应的转移函数组成。-sequence_dectect to six states, namely, six options the state machine. State machine of an extremely precise descr iption is that it is a directed graph, by a group of nodes and
decoder
- decoder code in verilog/vhdl language
main
- led灯控制，可以看到其灯灭和灯亮的现象-control, you can see its lights out and lights phenomenon led lights
mult_piped_8x8_2sC_h1
- 這是由我自己寫的8位元乘法器,雖然不是最好的但是希望能提供同學們課業上的好幫助-It was written by my own 8 yuan multiplier, though not the best but hope to provide better help students on academic
mod.verilog
- 计算两个数值间的最大公约数和最小公倍数。-calculate two numbers greatest common divisor and lowest common multiple.
mealy1
- mealy 状态机的独热编码源程序，接受么mealy状态机的编写规则。-mealy state machine of one-hot encoding source code, you mealy state machine to accept the preparation of the rules.
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
8-Bit-Up-Counter-With-Load
- 8位计数器，能实现加减计数，经过ise 测试仿真了。符合逻辑-8-bit counter, plus or minus count after ise test simulation. Logical