资源列表
sdh1
- 本段代码是关于SDH帧的操作的一段VHDL的代码。 主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame he
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
viterbi
- 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
multi_cpu
- 使用Verilog语言编写的多周期CPU,能实现CPU24条指令，-Using the Verilog language multi-cycle CPU, can achieve CPU24 instructions,
FullAdder
- This a code programed in Verilog Language. It is Full Adder code designed using Half Adder-This is a code programed in Verilog Language. It is Full Adder code designed using Half Adder..
Parking_plaza
- Parking_plaza Parking_plaza Parking_plaza-Parking_plaza Parking_plaza Parking_plaza Parking_plaza
inputoutput
- this code is simulation for input and output into VHDL, you can run at ModelSim and see the signal Wave
exer_vhdl_PWM
- 具有微处理器接口的PWMSG，周期和占空比均可调，感兴趣的可以自己扩展其他接口-Microprocessor interface PWMSG, period and duty cycle can be adjusted, interested can extend other interfaces
true_dual_port_ram_dual_clock
- Quartus II VHDL Template True Dual-Port RAM with dual clock
tx_module
- 串口通信，实现开发板与计算机之间的数据传输-A serial port communication, realizing the development board and the transfer of data between computers
Limi
- 用VHDL设计一个6位二进制计数器：用VHDL设计一个6位二进制计数器-VHDL design with a 6-bit binary counter