资源列表
RobustVerilog_free1.2_win
- RobustVerilog生成verilog工具-RobustVerilog version
clock
- 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
Car_drive
- 模拟汽车仪表板-由键盘去模拟控制汽车的油门、煞车、方向灯、大灯…等等。 由LCD去显示出目前的时速和档位。 LED模拟方向灯、大灯、转速表。 -Analog dashboard- from the keyboard to simulate the control of the car throttle, brake, turn signals, headlights ... and so on. By the LCD to display the current speed and
SDRAM_240T
- 本文档介绍了怎样用硬件编程语言VHDL语音编写SRAM的方法(This document describes how to write SRAM in a hardware programming language called VHDL)
DE2_115_SD_CARD
- DE2-115开发板SD卡驱动测试源码，对fpga开发者提供参考-DE2-115 development board SD card driver test source, provide a reference for fpga developer
verilog--bukezonghedeyuju
- 本文章总结了verilog语言中不可综合语句的具体情况，对于运用verilog HDL具有很大帮助-This article summarizes the verilog language is not comprehensive statement of the specific situation of great help using verilog HDL
FPGA
- FPGA入门系列实验教程，手把手教你学习FPGA-FPGA Starter series of experiments tutorial taught you to learn FPGA
uvm-1.0p1.tar
- Cadence 公司推出的高级验证语言，验证方法学开源-Cadence s introduction of an advanced verification languages, verification methodology open source
ad9226_verilog
- AD9226在Sparten6上的FPGA代码实现，测试通过。-AD9226 Sparten6 FPGA code on the test, the adoption.
matlab
- 完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry
Lab1
- Lab1 Altera about VHDL
DDS_SYS_CLK100M
- 基于FPGA的信号源设计，100M时钟，32位相位累加，能产生正玄波、方波，三角波，锯齿波，频率可调，频率范围0.03HZ-15MHZ。-FPGA-based signal source design, 100M clock, 32-bit phase accumulation can produce sine wave, square wave, triangle wave, sawtooth, adjustable frequency, the frequency range 0.03 Hz