资源列表
Matlab-Verilog-Linking
- Matlab Verilog Linking超級完整教學，可以-Matlab Verilog Linking super full of teaching, you can try
FPGA_DDS
- 用FPGA实现DDS双通道信号发生器，具有调相功能-With FPGA realizing double channel DDS signal generator, has the function of system.all
sdr_sdram_controller
- 使用verilog和VHDL实现 sdram_controller，代码清晰，测试过可以使用。-sdram_controller verilog vhdl
class12
- uart串口接收模块，对接收的数据串转并-Uart serial port receiving module, the received data string and turn
cpu_design
- 简单的CPU设计数字系统实验，使用的是精简指令，水平代码生成
caijing
- 这个是加密U盘的VHDL的源程序兼教学辅导，很具有实用性-U disk that is encrypted VHDL source program and coaching, it is practical
xapp485
- XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化
sdram_ok
- sdram + FPGA sdram + FPGA sdram + FPGA-sdram+ FPGAsdram+ FPGAsdram+ FPGAsdram+ FPGAsdram+ FPGA
pci_bridge
- 基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
8086FPGA
- xilinx ise 7.1下 实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
CLOCK
- 内含数字钟程序，程序准确，请大家放心下载-Includes digital clock program, the program is accurate, please rest assured download