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文件名称:pci_bridge

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.25mb
  • 已下载：
    0次
  • 提 供 者：
    敬***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
(系统自动生成,下载前可以参看下载内容)

下载文件列表

pci bridge/.svn/entries
pci bridge/trunk/.svn/entries
pci bridge/trunk/apps/.svn/entries
pci bridge/trunk/apps/test/.svn/entries
pci bridge/trunk/apps/test/bench/.svn/all-wcprops
pci bridge/trunk/apps/test/bench/.svn/entries
pci bridge/trunk/apps/test/bench/verilog/.svn/all-wcprops
pci bridge/trunk/apps/test/bench/verilog/.svn/entries
pci bridge/trunk/apps/test/bench/verilog/.svn/prop-base/test_bench.v.svn-base
pci bridge/trunk/apps/test/bench/verilog/.svn/prop-base/timescale.v.svn-base
pci bridge/trunk/apps/test/bench/verilog/.svn/text-base/test_bench.v.svn-base
pci bridge/trunk/apps/test/bench/verilog/.svn/text-base/timescale.v.svn-base
pci bridge/trunk/apps/test/bench/verilog/test_bench.v
pci bridge/trunk/apps/test/bench/verilog/timescale.v
pci bridge/trunk/apps/test/rtl/.svn/all-wcprops
pci bridge/trunk/apps/test/rtl/.svn/entries
pci bridge/trunk/apps/test/rtl/verilog/.svn/all-wcprops
pci bridge/trunk/apps/test/rtl/verilog/.svn/entries
pci bridge/trunk/apps/test/rtl/verilog/.svn/prop-base/pci_test_top_1clk.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/prop-base/pci_user_constants.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/text-base/pci_bridge32.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/text-base/pci_test_top_1clk.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/text-base/pci_test_top_2clks.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/text-base/pci_user_constants.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/.svn/text-base/test.v.svn-base
pci bridge/trunk/apps/test/rtl/verilog/pci_bridge32.v
pci bridge/trunk/apps/test/rtl/verilog/pci_test_top_1clk.v
pci bridge/trunk/apps/test/rtl/verilog/pci_test_top_2clks.v
pci bridge/trunk/apps/test/rtl/verilog/pci_user_constants.v
pci bridge/trunk/apps/test/rtl/verilog/test.v
pci bridge/trunk/apps/test/sim/.svn/entries
pci bridge/trunk/apps/test/sim/rtl_sim/.svn/entries
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/all-wcprops
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/entries
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/prop-base/clean.svn-base
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/prop-base/run_sim.scr.svn-base
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/text-base/clean.svn-base
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/text-base/run_sim.scr.svn-base
pci bridge/trunk/apps/test/sim/rtl_sim/run/.svn/tmp/text-base/vsim.wlf.svn-base
pci bridge/trunk/apps/test/sim/rtl_sim/run/clean
pci bridge/trunk/apps/test/sim/rtl_sim/run/run_sim.scr
pci bridge/trunk/bench/.svn/all-wcprops
pci bridge/trunk/bench/.svn/entries
pci bridge/trunk/bench/verilog/.svn/all-wcprops
pci bridge/trunk/bench/verilog/.svn/entries
pci bridge/trunk/bench/verilog/.svn/prop-base/pci_blue_constants.vh.svn-base
pci bridge/trunk/bench/verilog/.svn/prop-base/pci_blue_options.vh.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/i2c_slave_model.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_behavioral_pci2pci_bridge.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_behaviorial_device.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_behaviorial_master.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_behaviorial_target.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_bench_common_tasks.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_blue_arbiter.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_blue_constants.vh.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_blue_options.vh.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_bus_monitor.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_regression_constants.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_testbench_defines.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/pci_unsupported_commands_master.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/system.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/top.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/wb_bus_mon.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/wb_master32.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/wb_master_behavioral.v.svn-base
pci bridge/trunk/bench/verilog/.svn/text-base/wb_slave_behavioral.v.svn-base
pci bridge/trunk/bench/verilog/i2c_slave_model.v
pci bridge/trunk/bench/verilog/pci_behavioral_pci2pci_bridge.v
pci bridge/trunk/bench/verilog/pci_behaviorial_device.v
pci bridge/trunk/bench/verilog/pci_behaviorial_master.v
pci bridge/trunk/bench/verilog/pci_behaviorial_target.v
pci bridge/trunk/bench/verilog/pci_bench_common_tasks.v
pci bridge/trunk/bench/verilog/pci_blue_arbiter.v
pci bridge/trunk/bench/verilog/pci_blue_constants.vh
pci bridge/trunk/bench/verilog/pci_blue_options.vh
pci bridge/trunk/bench/verilog/pci_bus_monitor.v
pci bridge/trunk/bench/verilog/pci_regression_constants.v
pci bridge/trunk/bench/verilog/pci_testbench_defines.v
pci bridge/trunk/bench/verilog/pci_unsupported_commands_master.v
pci bridge/trunk/bench/verilog/system.v
pci bridge/trunk/bench/verilog/top.v
pci bridge/trunk/bench/verilog/wb_bus_mon.v
pci bridge/trunk/

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