资源列表
并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)
- 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
log_verilog
- 使用cordic方法计算log，verilog语言实现(Calculate log, verilog language using cordic method)
GPU in VHDL
- 这是一篇关于在可编程逻辑器件（CPLD）上实现一个8 比特的图形处理器GPU的报告-This report is about how to achieve an 8-bit graphics processor GPU on the programmable logic device (CPLD).
Sawtooth
- 在Altera DE2-70的开发板上实现产生锯齿波信号。-In the Altera DE2-70 development board realize sawtooth signal.
M_generation
- 伪随机序列发生器，即M序列发生器，VHDL语言完成，已仿真通过。-Pseudo-random sequence generator, VHDL language completed, through simulation.
jiaotongdeng
- 通过并行接口8255实现十字路*通灯的模拟控制,进一步掌握对并行口的使用。-Crossroads traffic lights analog control via the parallel interface 8255, and further understand the use of the parallel port.
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
1111
- 基于Verilog-HDL的转子振动噪声电压峰值检测，值得学习啊，
sin
- 在Altera DE2-70的开发板上实现产生正弦波信号。-Achieve generate sine wave signal at Altera DE2-70 development board.
HDMI_test
- HDMI显示数字钟，把之前编写的数字钟程序用HDMI接口显示在电子屏幕上-HDMI display digital clock, digital clock to before you write a program using HDMI interface displayed on the electronic screen
Rectangular-wave
- 在Altera DE2-70的开发板上实现产生矩形波信号。-In the Altera DE2-70 development board to achieve a square wave signal generated.
taxi
- 关于计程车的计费系统，可以显示路程和所收费用-Billing system on a taxi, you can display distance and the fees