资源列表
PLL_1
- Phase lock loop generation for vhdl (DE2 board)
sine_wave_2011_0329
- 正弦波波形发生器，verilog编写，Modsim仿真。-sine wave genonter
FPGA.rar
- FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计,FPGA, vhdl language learning materials FPGA design of a simple design dds
DSSS
- 基于FPGA的我直接扩频序列发射机的quarters代码，-direct sequence transmitter
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
keypad
- 4*4的薄膜按键，采用状态机实现译码功能和按键消抖功能(4 * 4 of the film button, using the state machine to achieve decoding and key function)
DDS
- DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，
lab1
- chuc cac chu vui ve voi dong tai lieu nay nhe
08_eeprom_test
- eeprom相关FPGA程序VHDL源代码，可直接用！用ISE打开！-eeprom related FPGA program VHDL source code, can use directly!Using ISE open!
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
square_wave
- 利用Vivado的高层次综合实现了一个可调方波的HDL描述-use the Vivado to realize a square wave with adjustable period