资源列表
dds
- 利用altera的cyclone FPGA芯片，模拟DDS原理，产生频率可调的正弦波，并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, analog DDS principle, have adjustable frequency sine wave, and use the built-in logic analyzer simulation success
fpu100_latest.tar
- Features - FPU supports the following arithmetic operations: - Add - Subtract - Multiply - Divide - Square Root
FPGA-based-PWM-generator
- 基于FPGA的PWM发生器，将所需的正弦波和三角波转化为数据文件，存入存储器中，用计数器逐一读取产生波形-FPGA-based PWM generator, the desired sine wave and triangular wave into a data file into memory, and one by one to read the counter generates a waveform
lcd
- lcd驱动，本代码仅供交流学习，未经同意不得用于其它商业用途。-beng daima
text
- fpga锁相环实验——锁相环使用，开发环境为Quartus II -The fpga- phase-locked loop using phase-locked loop experiment, development environment for the Quartus II
IIC-fpga-verilog
- 基于fpga的IIC设计，verilog-IIC fpga-based design, verilog
DE2-usb-isp1362-2007-08-18
- USB host project with Altera DE2
AD9851
- 控制AD9851输出频率 控制AD9851输出频率 -control ad9851 frequence
Programmable-Logic-Controllers
- Programmable Logic Controllers
lab7_2_new
- 移动信息工程学院实验课程源码：用FSM实现soda_machine(自动售货机)-Use verilog to implemwnt a soda_machine
SD
- Altera DE0 FPGA的SD卡读取程序，强力推荐！ -Altera DE0 FPGA SD card reader, highly recommended!
CycloneIII_EP3C40F780C8_38_TS_Paint
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,TS_Paint实验代码 -SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, TS_Paint code