资源列表
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
install_flash_player_ax
- 讲解了很多niosii 的基础知识 可以帮助初学者学习-Explain the basics of many niosii can help beginners learn
dppramm
- 基于fpga的双口ram的设计与实现，好东西，希望大家喜欢-The dual-port ram fpga based design and implementation of good things, hope you like
software-engineering
- software engeneering UML diagrams wish help u alot
halfadder
- vhdl code for halfadder
uart
- RS232串口调试程序，已经经过试验和调试，很方便，带注释-RS232 serial debugger
VERILOG_VLSI_LAB_MANUAL
- VHDL Lab Manual useful for lab purpose
modelsim
- modelsim是在FPGA开发中很重要的时序仿真辅助工具，其中包含了对modelsim这个软件很详细的使用所用说明。使你非常简单的就学会了！-modelsim is a very important development in the FPGA timing simulation aids, which contains details of modelsim use of this software is used for instructions. Make you a very sim
ram
- ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
DE2_LCM_TV
- 该模块是应用于针对DE2平台设计的LCM模块TRDB_LCM。其功能是将TV视频解码器输出的数据直接送到LCM上显示。-This module is used in the design for the DE2 platform LCM module TRDB_LCM. Its function is to TV video decoder output data directly to the LCM display.
DE2_115_Audio
- NIOS2 实现音频代码,录音，听到声音-NIOS2 Audio
wave_gen_vhd_s6
- 波形发生器，可以产生需要的波形，根据你的需要改变波的频率或者其他参数-as the same as its name