资源列表
MIPSCPU_Pipeline
- 流水线的设计，基于mips流水线的管道设计-Pipeline design, pipeline design based on mips pipeline
AD7606URAT
- AD7606 FPGA du chegnxu -AD7606 .V FPGA du chegnxu
C20_BGA_USB
- USB通讯，驱动程序，FPGA VHDL-USB communication, the driver, FPGA VHDL
QPSvhdl
- QPSK的vhdl调制与解调，一篇论文，讲解很详细，并附带VHDL仿真设计程序-The vhdl QPSK modulation and demodulation, a paper to explain in great detail, and design program with VHDL simulation
FPGA
- 用于FPGA routing and placement, 在research 中多应用。 文件包括data structure 和程序源代码-FGPA research project based on the FPGA routing and placement
table-tennis
- vrilog语言编写，使用状态机模拟乒乓球运动-vrilog language, using the state machine simulation table tennis
ISE-12.3-Guide
- 本文为ise12.3详细开发步骤，对新手会非常有帮助的。-This article ise12.3 detailed development steps, the novice will be very helpful.
DW_apb_timer
- verilog实现计时器timer，可直接用于芯片开发中。-verilog achieve timer, it can be directly used for chip development.
DW_APB_TIMER_2.05A_2010
- DW_APB_TIMER_2.05A_2010
ddsdds
- 直接数字频率合成，可以直接输出所需要的波形-Direct digital synthesizer, you can direct output of the waveform required
the-strong-cpu-design
- 增强型CPU设计，带有PC指针与存储器，用VHDL语言写的，不含流水线设计，实现二进制灯循环亮-Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
vhdl
- VHDL的经典教程，深入浅出，对VHDL的入门很有帮助-VHDL Tutorial classic, easy, helpful entry on the VHDL