资源列表
digital_clock
- 数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。-Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ct
i2c_altera
- I2C总线控制器 altera公司提供VHDL实现代码
61EDA_C2714
- xilinx ISE 4.1的入门，简单简单的。看看看看！-xilinx ISE 4.1, entry, simple simple. Look look!
8051 Verilog Code
- 8051 Core Verilog RTL code
mouse_kit
- 实现难度可调（6级，速度不同）的简单打地鼠游戏。开发板上的led灯代表地鼠，按键代表锤子。此程序代码可直接执行，适合初学者VHDL入门。 源码中，divider为分屏器；key_scan为按键扫描；random产生随机数；music为背景音乐播放模块；manage为主程序模块。-Adjustable implementation difficulty (6 level, different speeds) simple whack-a-mole game.The led lights on
8051Core
- 8051 Core Verilog RTL IP Code
DE2_SD_Card_Audio
- 基于SD卡音乐播发器设计代码,SOPC技术,功能齐全的,编译成功的代码-Based on the SD card music broadcast design code, SOPC technology, full-featured, compile the code successfully
duogongnengshuzizhong
- FPGA开发实例 之 多功能数字钟.多功能数字钟应该具有的功能有：显示时－分－秒、整点报时、小时和分钟可调等基本功能。-FPGA development instance of multi-function digital clock. The function of the multi-function digital clock should have are: show- points- second, hour, hour and minute basic function such a
lcd_vhdl
- 这是液晶的VHDL版写的驱动程序，能够控制1602液晶的显示-This is the LCD diver code that is written by vhdl
traffic_lights
- Verilog语言3个程序，包括4位二进制的BCD码加法器，ALU位片，交通信号灯。既有源码也有word文档说明。-Verilog language three procedures, including 4-bit binary code of the BCD adder, ALU-bit chip, traffic lights. Only source documents that have word.
FPGA-HDLC-design
- 基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf
cnt10
- 这是一个使用vhdl语言编写的fpga代码，它能够实现0-9之内的计数功能。-This is a use of the VHDL language fpga code, it can achieve the 0-9 count.