资源列表
Drive-ADS8365-state-machine
- 驱动ADS8365状态机,Quartus II Verilog-Drive ADS8365 state machine, Quartus II Verilog
canbus
- can总线的开发和设计，基于FPGA，很强大-can bus development and design, based on FPGA, very powerful
bijiaoqi
- verilog 9位数 3乘3 窗口比较器
Drivers_USB_TELIUM-PC
- usb ingenico driver EFT930 for win xp
logic_app
- 中际赛微15期培训班 逻辑功能试验 2009-5-Competition in 15 micro-logic function tests training 2009-5
rapport_vhdl
- Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone -Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone II
ISCAS85aISCAS89
- Verilig of ISCAS85 and ISCAS89
Principles-of-Verifiable-RTL-Design
- RTL设计的基本方法，帮助掌握RTL编码方法-RTL
RGB
- 用VHDL语言实现将Bayer格式图片转为RGB格式图片-The function of the program is to transfer the Bayer picture into RGB picture
SegSimplified
- 本工程使用verilog HDL和vivado2014集成开发环境实现利用xilinx Basys3开发板上4位数码管显示从0到9999的计数器功能。-This project uses verilog HDL to realise counting 0 to 9999 on the 7-seg LED loaded on Xilinx Basys3 board.
exp1_CountWithMemory
- 用Altera—DE2板实现秒表的功能，该秒表具有一个复位按钮，两个暂停按钮和两个记录按钮。-Stopwatch function using Altera-DE2 board, the stopwatch has a reset button, two buttons and two recording pause button.