资源列表
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
ads1252
- 用fpga控制ads1252采样，晶振高，速度快，采用的是同步模式，采样回来的前5个值不准，取值要从第6个值开始，第一位是标志位-With fpga control ads1252 sampling, crystal, high speed, using the synchronous mode, the first five sampling returned values are not allowed, ranging from the first six va
MATLAB
- 用matlab生成mif文件，分别用两种不同方法，操作简单，实验好用-Mif file generated using matlab, respectively, with two different methods, simple operation, easy to use test
DLX-pipeline-in-verilog
- verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
fpga_sdram_inst
- nios学习资料，fpga调用外部sdram实例，值得初学者下载。-nios learning materials, fpga call external sdram instance, it is worth beginners to download.
I2C_i2c
- fpga例程：用fpga实现i2c串口通讯的vhdl详细代码，完整的quartus工程，可直接用-fpga routines: i2c serial communication with fpga implementation details of vhdl code, complete quartus project, can be directly used
uart_serial_vhdl
- fpga例程：用实fpga现uart串口通讯的vhdl详细代码，附一个串口通讯助手小插件-fpga routines: solid fpga vhdl now uart serial communication code in detail, with a small plug-in serial communications assistant
uart_VHDL
- VHDL写的串口程序，调试通过，有兴趣的朋友可以看一看-VHDL write serial programs, debugging through, interested friends can look at
state
- 简单状态机数码管显示,Quartus II VHDL设计语言-Asimple state machine digital tube display, Quartus II VHDL design language
tmx
- LCD显示频率计,Quartus II VHDL设计语言-LCD display frequency meter, Quartus II VHDL design language
state_machine
- 状态机控制步进电机,Quartus II VHDL设计语言-The state machine control stepping motor, Quartus II VHDL design language
led_0_7
- 八位数码管动态显示0-7,Quartus II VHDL设计语言-Eight digital tube dynamic display 0-7, Quartus II VHDL design language