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Document
- vhdl code for 5509a evm
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
part3
- part 3 lab 2 vhdl altera
liangzhu
- 设计一个能演奏梁祝的电子琴。要以写入其它的乐曲进行演奏-Butterfly design a can play the keyboard. To write music to be performed other
A-QuanJia-device-design
- 一位全加器设计，，二进制设计，，同步二进制计数-A QuanJia device design
ddsaom-200M
- 直接频率合成器 (DDS)ad9954 单点频功能程序，利用单片机控制ad9954,通过串口设置不同频率字，即可设置不同的频率。-Direct frequency synthesizer (DDS) ad9954 single frequency function procedures, the use of single-chip control ad9954, set a different frequency of the word through the serial port, you
DigitalCompinacijaSimulacija
- It is a bridge between CPU and sensors where user can not connect sensors directly on CPU. It consumes very small number od LUTs and it is suitable for CPLD design. it works on following way, when logic detects falling edge of RX, then this action tr
multiplexers
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
fifo1616
- FIFO先入先出堆栈，包括三个子程序，可根据需要选择-FIFO first in-first stack, including three subprogram, according to choose
edapinluji
- 接通电源，可以测输入的频率，显示在数码管上。-Switch on the power, you can measure the input frequency, displayed on the digital pipe.
submodule
- verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均-verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count
code
- VHDL实现的LAPS协议实现的（LAPS：Link Access Procedure-SDH（SDH 上的链路接入规程））。包括发送机和接收机的程序-VHDL implementation of LAPS protocol implementation (LAPS: Link Access Procedure-SDH (SDH Link Access Procedure on)). Including procedures for transmitter and receiver