资源列表
控件移动.rar
- 控件移动.rar
pinlvji
- 课程设计-数字频率计 能够很好实现频率计功能
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
usb_Blaster_rev_B_code
- 俄罗斯电子论坛上流行的USB_Blaster_rev_B 代码。功能不用多说，好东西大家一起分享，
zmm_AD9218
- adi公司的ad9218的verilog程序，调试通过！谢谢指正-verilog program for the the adi company ad9218, through debugging.Thank correction
VHDL-Lock
- EDA的课程设计资料，欢迎大家下载。 基于VHDL的电子密码锁的设计-EDA design data of course, welcome to download. VHDL-based design of an electronic lock
lpc_peri
- LPC periph，VHDL and verilog version design， lattice
inface
- 一种接口控制板的逻辑电路设计CPLD程序。-an interface to the control board CPLD logic circuit design process.
8-Bit-Up-Counter-With-Load
- 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter
uart
- 使用VERILOG实现自己定以的UART算法，只要自己看懂了，再修给下下就可以使用了-VERILOG use to achieve their own set of UART algorithm, as long as my understood, and then repair to the next can be used under
case-and-if-programing-in-verilog
- Case语句和if语句在电路设计中的注意事项，各种产生锁存器的原因分析，以及原代码-case and if using in verilog
DDS_Adder
- DDS加法程序，用verilog程序写成，在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s