资源列表
8位相位相加乘法器
- 8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
i2c_master_bit_ctrl
- i2c core : master bit control
vergleiche
- 32为比特数据比较器，讲高电平位不断右移，直到左边全为0，右边全为1-32-bit data for the comparator, high-bit been right about, until the whole left side is 0, the right of all to 1
statemaschine
- 5状态状态机，1为计数器，2为锁存器，3为向上加一，4为向下减3,5为停止技术在输出为10的时候-5 state state machine, 1 counter, latch 2, 3 plus one up, 4 down to minus 3,5 to stop technology, when the output is 10
ps2lab1
- hex file gen you can get this in any way do it and enjoy it
FPGANOV
- spartan3e 开发板上 ADC AMP DA芯片的控制代码 vhdl-ADC AMPDA control codes on spartan3e kit board
xilinx_ise_12
- 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
eiush
- Based on multi-document image obtained combining technique, Consider shadow rain attenuation and multipath effects Rapid expansion of random spanning tree algorithm.
fifo
- 一个FIFO产生程序，主要是一个格雷码的加法器-A FIFO generation process, is primarily a gray code adder
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
xilinx_count
- 关于xilinx环境下的电路设计，验证计数器电路的正确性-About Xilinx design environment, verify the correctness of counter circuit
控件移动.rar
- 控件移动.rar