资源列表
step_motor
- 步进电机定位控制系统VHDL程序,可以进行步进角的倍数设定,激磁方式的选择
soc-count
- soc 的 vhdl语言设计的基于嵌入式 数字钟-soc vhdl language design based on embedded digital clock
Vrilog-hdl--Sequence-check.doc
- 用VrilogHDL编写的一个序列检测器-use rilogHDL define a Sequence check Instrument
uart_verilog
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
ETH
- 该系统通过顶层模块，调用4底层模块实现。4大模块底层模块为：cpu模块、发送模块、接收模块、mii模块-The system top-level module, called the bottom module 4. 4 large modules underlying module: cpu modules, transmit modules, receiver modules, mii module
8.24
- 步进电机定位控制系统VHDL程序与仿真,程序中有详细注释-Stepper motor positioning control system procedures and VHDL simulation procedures detailed notes
PLI
- VCS下编译通过的PLI的实例，包括功能仿真，和可综合代码-VCS compiled under the pli example, including the functional simulation, and integrated code
RS232_to_RS485
- RS232_to_RS485 converter on VHDL
a_good_game
- 用vhdl语言编写的一个小的游戏-Vhdl prepared with a small game
pwmyixiang
- 用VHDL编写的基于CPLD移相程序,开发环境是ISE9.1-CPLD with VHDL-based preparation phase procedures, the development environment is ISE9.1
rs_encoder
- reed solomon encoder used in DVB verilog code.
hola mundo2
- hat the image I was created by convolving a true image with a % point-spread function PSF and possibly by adding noise. The algorithm % is optimal in a sense of least mean square error between the % estimated and the true images