资源列表
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
UART
- uart通用异步收发器，包括收发模块和。数据产生模块-uart transmit and reciver
fft_32k
- FFT 32k use VHDL MATLAB
i2cEEPROM.rar
- 使用VHDL编写的操作EEPROM来控制iic的读写操作，很方便,Use VHDL to prepare the operation to control the IIC EEPROM read and write operation, it is convenient
11.ppt
- THIS USEFULL FOR VLSI-THIS IS USEFULL FOR VLSI
vhdl_16CPU
- 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
6040404
- Signal generator final report
Altera-verilog-DS1302_ok
- Altera开发板上面，运行OK的DS1302程序；(Altera flatform, dirve ds1302 device, test ok.)
example19-LCD1602
- 基于verilog HDL的LCD1602显示程序，调试通过，可直接调用。-Based verilog HDL of LCD1602 display program, debugging through, can be called directly.
ise
- 设计微处理器基本输入输出系统，实现投票系统，通过拨码开关（SW0~SW3）输入，当BTN North (V4)键被按下时收集投票。若投票数大于或等于3票，则点亮板上的LD0，并在超级终端输出“Pass!”。若投票数小于3票，则不点亮LD0，并在超级终端输出“Lose!”-Design microprocessor basic input output system, voting system, input via DIP switch (SW0 to SW3) to collect the b
finaldesign_watch
- 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for th
example17-DS1302_ok
- FPGA verilog HDL开发的时钟芯片DS1302程序，调试可用。-FPGA verilog HDL developed clock chip DS1302, debuggers are available.