资源列表
XD-D01-20110108
- 压缩感知是近几年比较热门的话题，其中我研究的双像素相机就是基于DMD光调制系统和它-Compressed sensing is more popular in recent years, the topic, which I studied double pixel camera is based on the the DMD light-modulation system and
mem-opt_final
- memory optimisation cache memory, RAM,SRAM, main memory related doc and ppt attached
MAXplusII_
- maxplus2 的功能达介绍 让你更加 熟练使用这个软件 更加清晰-maxplus2
clock
- 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
wangyong
- 用VHDL实现数字钟编码 ，这里是所有源代码和报告-output a digital clock
Experiment03
- FPGA黑金开发板实验教程，实验3的源代码。实验手册见《verilog那些事儿》-Black gold FPGA development board test tutorials, experiment 3, the source code. Laboratory manual, see " verilog that thing"
fft_32K
- This example describes a 32K-point fast Fourier transform using the Altera FFT IP MegaCore. 描述了一个32K的点快速傅立叶变换（FFT） 。
xin
- 实现乘法，8位的乘法功能，比较简单实用，能够实现控件开始运算-Achieve multiplication, 8-bit multiplication function is relatively simple and practical, to start operations to achieve control
fpga-study
- 学习CPLD/FPGA很好的电子书．讲得很好．-Learning CPLD/FPGA good books. Put it very well.
usbsample
- 基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
sap1
- SAP 1 ARCHITECTURE.HOW TO IMPLIMENT USING VERILOG-SAP 1 ARCHITECTURE.HOW TO IMPLIMENT USING VERILOG