资源列表
yufafenxiqi
- 该程序能求出任意给定的文法的所有非终极符和终极符的first集，所有非终极符的follow集，所有语句的select集，能求出能导空的非终极符集合。给定任意字符串该程序能判定出是否能接受。由于空符号不好输入，在程序中用到空符号全部用@表示。-The program can calculate any given grammar of all non-ultimate breaks and the ultimate symbol of the first set, all non-ultimate
booth
- Booth multiplier to multiply 12 bit number
zidongshouhuoji
- 自动售货机的VHDL代码，包括选商品，出货，退货，找零等功能-The VHDL code for a vending machine, including the selection of goods, shipping, returns, Keep the change and other functions
delay_early_gate.rar
- 超前滞后锁相环，可以精确的是想符号同步的 采用V_LOG代码编写 可以直接使用,Lead and lag phase-locked loop can be accurate is to synchronize the use of symbols V_LOG code can be directly used to prepare
Source-code-(all)
- direct sequence to generate sine code for altera
msttr
- msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
verilog_18bit_Div
- verilog编写的18位输入高精度的除法器，带说明文件和测试代码。-18 input precision divider verilog prepared with documentation and test code.
VGA Output
- VGA Timing Output display
sqrt_for_single_float_point
- 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
verilog_uart
- verilog实现串口的调试，用串口调试助手验证通过。-verilog serial debugging and validation by serial debugging assistant.
vga_timing_vhdl
- Timing generator for displaying graphics on a VGA screen in VHDL
exp_code
- Hi useful exponential code in vhdl