资源列表
div_freq
- 一个数字频率计。利用VHDL实现。有3个VHDL文件组成。其中div_fre为顶层文件-A digital frequency meter. Use of VHDL implementation. There are three VHDL files. One of the top-level document div_fre
h264intra4x4
- H.264 intra predication
NIO-II-function
- NIOS II常用函数详解详细讲解了NIOS II中各种函数的使用方法-NIOS II explain commonly used functions on the NIOS II in detail in the use of a variety of functions
NIOSII
- niosII常用函数介绍，对研究NIOS的人员很有帮助-niosII commonly used functions introduced the study of NIOS staff very helpful
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
matlab
- matlab中的无线信道仿真与实现。欢迎分享，分享快乐。-The wireless channel simulation and realization in matlab.Welcome to share, share the happiness.
step-moto
- 步进电机 细分/非细分 verilog -Stepping Motor/Non subdivision verilog
src
- 基于VHDL的4*4矩阵按键识别，按键与LED相对应，每按一个按键，对应LED亮一次。-Corresponding VHDL-based 4* 4 matrix identification keys, buttons and LED, each press of a button, the corresponding LED lights up again.
Frame_2D
- 自己编写的通用2维框架结构，可以计算模态、静力、动力响应-A 2D frame building of ANSYS developed by myself, can calculate modal, static and dynamic response
Inter_Rom
- 交织器（用LDPC译码，H矩阵交织器书写方法）希望有用-Interleaver (with LDPC decoding, H matrix interleaver write methods) seek to help
counter
- 一个基于占空比1：1的10-400分频的计数器，很好用，可随意设置-A duty cycle of 1:1 10-400 points based on frequency counter, useful, free to set up
67_ellipf
- 五阶椭圆滤波器硬件描述 使用VHDL语言 注释十分详细 想要的赶紧下载吧-Fifth-order elliptic filter using VHDL hardware descr iption language Notes very detailed you want to download