资源列表
clk_DCM_50to75MHz
- 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency mult
i2c_latest.tar
- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the assoc
Layman-FunFPGA(1-150)
- 特权同学的深入浅出玩转FPAG文档，1-150，书籍电子档-Fun FPAG privileged students layman documentation ,1-150, E-book file
VerilogBook
- 详细解析了verilog语言的语法知识，适于入门学习使用，学习掌握verilog语言-Detailed analysis of the verilog language, grammar, suitable for entry-learning, learning and mastering the language verilog
srio_test_1
- xilinx rapidio仿真,xilinx ip core 改核为收费核，用liscense获取核文件，共享个大家学习-xilinx rapidio
CIC_filter_implement
- 实现CIC抽取滤波器，在多速率通信中经常需要用到的CIC抽取滤波器-CIC decimation filter implemented in the multi-rate communications often need to use the CIC decimation filter
FIR_FILTER
- FIR滤波器的verilog实现，包含testbench，以及设计文档，文档里面详细介绍了滤波器系数的求取-FIR filter verilog implementation, including testbench, and the design document, the document which details the filter coefficients to strike
diantiyunxing
- 能够实现电梯的基本运行功能，其中分为四个模块分开实现。-To achieve the basic operation of the elevator function, which is divided into four modules are implemented separately.
fenpin5
- 用verilog语言实现的分频器，开发环境是Quartus2 7.2版本-Divider using verilog achieve
encoder
- 8线-3线编码器，用verilog语言实现的-8 lines-3 line encoder, using verilog language
confirmpulse
- 可调频率的脉冲信号发生器，占空比为50 -Adjustable frequency pulse signal generator, the duty cycle is 50
clk_div
- 任意频率脉冲可调，同时占空比为定值50 -Arbitrary frequency pulse adjustable, while 50 of the duty cycle is constant