资源列表
4weiquanjiaqi
- 4位全加器由3个模块构成。首先，通过实例引用基本门级元件xor、and定义底层的半加器模块halfadder，接着实例引用两个半加器模块halfadder和一个基本或门元件or组合成为全加器模块fulladder，最后实例引用4个1位的全加器模块fulladder构成4位全加器的顶层模块-4 full adder by the three modules. First, the basic gate-level component instance references xor, and def
jiancedianlu
- 功能是检测出串行输入数据Sin中的4位二进制序列0101（自左至右输入），当检测到该序列时，输出Out=1；没有检测到该序列时，输出Out=0。-Function is to detect the serial input data Sin the 4-bit binary sequence 0101 (from left to right input), when the sequence is detected, the output Out = 1 the sequence is not
_50MHz--1Hz
- 分频电路，可将DE2板子上的50MHz分为1Hz输出，绝对可行，附有仿真程序！-Divider circuit can be divided into the DE2 board 1Hz output on 50MHz, absolutely feasible, with a simulation program!
baker-code-generator
- 巴克码发生器,VHDL语言描述,可以在quartus II上运行，基于altera-baker code generator
eetop.cn_quartus_pgm
- verilog基本语法 入门的视频教程 flash的-verilog basic syntax of introductory video tutorials flash
eetop.cn_quartus_design
- verilog基本语法 适合入门学习 视频讲解-The basic syntax for entry-learning verilog video to explain
div_freq
- 使用Altera的FPGA开发的频率合成器，实现输入频率的二等分、四等分、八等分等。-Altera' s FPGA development using a frequency synthesizer, the realization of the input frequency halved and quartered, eight equal portions and so on.
shizhong_xianshi
- 使用Altera型FPGA的数字时钟，使用按键显示，具有调时计时功能-Using Altera FPGA-based digital clock, using the key display, with timing function when adjusting
pinlvji
- verilog 简易频率计的设置，包括整个工程-verilog simple frequency meter settings, including the entire project
LPM_RAM
- verilog 参数可设置调用模块RAM-verilog parameter can be set to call the module RAM
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
shixukongzhi
- verilog 时序控制模块 做频率计时使用。-verilog timing frequency timing control module used to do.