资源列表
ok--lcd2
- sparten 3e lcd 驱动程序。数据通信线为4个-sparten 3e lcd driver. Data communication lines 4
quartus
- Quartus II使用教程，Quartus II是Altera公司推出的CPLD/FPGA开发工具，Quartus II提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性-Quartus II using the tutorial, Quartus II Altera Corporation launched CPLD/FPGA development tool, Quartus II development kit provides a fully integrated
mux2to1
- 2路选择器 很好很使用的VHDL语言 能够快速的解决问题-2-way selector
ps_transfer
- verilog HDL语言编写的8位并串转换，使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ，can comprehense
des1
- 对称密码算法des的Verilog语言实现，已经测试通过。欢迎下载！-Symmetric cryptographic algorithm of des Verilog language implementation, has the test pass. Welcome to download!
Matlab-verilog
- 《无线通信FPGA设计》一书中例子的Matlab及verilog代码-The example Matlab FPGA design of wireless communication, " a book and verilog code
SDR-SDRAMverilog
- 经典三星SDR SDRAM读写verilog代码分享-Classic Samsung SDR SDRAM read and write verilog code share
vga1
- 基于赛灵思的ISE实现的VGA驱动模块，仿真通过-Based on the Xilinx ISE realized VGA driver module, through simulation
halfaddersch
- halfadder sch vhdl code
4-1Multiplexer
- mux 4x1 wire command verilog code
zongxianchuanshu
- 湖南大学总线传输实验 原理图及仿真结果-Hunan University bus transfer experimental experimental schematics and simulation results
VHDL
- 基于VHDL语言的交通灯设计:通过状态机设计实现交通灯的红黄绿三种灯显示.其功能包括:红绿黄灯显示,倒计时功能,测试功能,手动控制功能.-Based on VHDL design of traffic lights: red, yellow, and green traffic lights, three lights through the state machine design features include: red, green, yellow, countdown function