资源列表
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
UART_TX
- UART收发，verilog语言，测试成功-UART transceiver, verilog language, the test is successful
FPGA-dianziqin
- FPGA电子琴的源代码的描述，非常的好，同学们如果需要请下载-Descr iption of the FPGA source code of the keyboard is very good, students need to download the
Adder32Bit
- Adder 32 bit in MIPS microprocessor.
Mux32to1
- mux 32 to 1 verilog code. It may be good for you !
Mux8to1
- mux 4 to 1 verilog code. It may be good for you !
mux2to1
- mux 2 to 1 verilog code. It may be good for you !
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
good
- FPGA电机电流矢量控制程序,用vhdl语言编写-vector control IP in vhdl for fpga
Verilog123
- cpld 实现于电脑的串口通信，跟大家分享下-The cpld realize on the computer' s serial port communication, to share with you the next
uart_Rx
- 在Xilinx的SP605开发板上实现了FPGA接收数据的串口通讯，接收数据是Led会亮，没有接收数据的时候灯是灭的。-Xilinx SP605 development board FPGA receives serial data communication receive data Led lights not receive data when the lights are off.
Dos_Pro---8.18
- 简易数字示波器，从AD接受双通道数据，存入内部fifo，并通过串口传至单片机实现波形显示-Simple digital oscilloscope, from AD to accept dual-channel data stored in the internal fifo waveform display and transmitted to the microcontroller through the serial port